As some of you have noticed, the internal RAM in the 图16F appears to be arranged in “banks”. Each bank holds 128 RAM 寄存器 total. The first 128 RAM 地点 are in bank 0, the next 128 RAM 地点 are in bank 1, so on and so forth.
但是等一下…is this REALLY the case? If it is, then why is it 那 when we indirect 地址 via the FSR pointer register 那 we can access 256 RAM 地点 without having to bank select?
因为这不是’t what’s really going on.
iRAM on a 图16F is a contiguous space. It starts at 地址 0x000 and ends at 0x1FF. However, some 地点 within this space are unimplemented. The datasheet states 那 iRAM is divided up into 4 banks of 128 寄存器 each. Why is this?
The reason is because there is a limitation in the instructions 那 the PIC uses to 地址 iRAM 地点 (basically all of the instructions which have an “f” in them). 通过 te-oriented instructions which 地址 the 寄存器 are in the format of –
公告AD0-AD6…that’s only 7 地址 bits!
Basically, instructions which directly 地址 the iRAM register 地点 can only provide 7 of the 地址 bits. Since 7 bits can only count to 0x7F (decimal 127), this limits the instruction itself to only access 128 RAM 地点 on its own…因此限制。
So how can we overcome the limitation so 那 we can 地址 the entire iRAM space? With the addition of two more bits of course, but where would they come from?
简单…the STATUS register!
We’ve all heard them referred to as the “bank select” bits but this is just a convention 那 Microchip decided to use for its “register 银行业” concept. Bits RP1 and RP0 (Register Page 1 and Register Page 0 respectively) serve as the upper 2 地址 bits for instructions which directly 地址 the iRAM 地点.
So say for instance we wanted to move a value in W to register TRISA, which has iRAM 地址 0x85 (b’010000101). The instruction could not supply the leading “01” in the 地址, so these two bits must come from register bits RP0 and RP1. So prior to writing the contents of W to register TRISA, we must first execute these two instructions –
这使RP1位为0，而使RP0位为1，这使我们在TRISA中以“ 01”开头’s 地址.
Now we want to write to PORTA, which resides at iRAM 地址 0x05 (b’000000101′）。现在必须清除前两位以访问位置0x05–
With indirect 地址ing using the FSR register, we only need 1 more bit. This is because the FSR is an 8 bit register so it can 地址 up to 256 iRAM 地点 on its own. Its 9th bit comes from bit IRP (Indirect Register Page) in the STATUS register.
With a more conventional processor like the Intel 8051, a mov instruction is 8 bits long, followed by 1 or 2 more bytes 那 provide the 地址(es) 那 the mov instruction is being executed on. With an instruction set of this nature, no iRAM ‘banking’是必须的。但是，由于PIC是具有单个14位指令字的RISC处理器，因此可以完成的工作以及必须完成的工作将受到限制，这就是其中之一。
If we were to use the FSR to indirectly 地址 register TRISA, we could simply load the FSR with the value of 0x85, load W with the immediate value to write to TRISA, then load the value in W into the INDF register without having to bank select. This is because register FSR is an 8 bit register and can supply 8 of the 9 地址 bits on its own. However, we must ensure 那 bit IRP in the STATUS register is clear prior to doing this otherwise we would end up writing to iRAM register 地址 0x185 instead of 0x085.
所以你有它…PIC 16F register 银行业 explained.