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辛普西辛

SOC体彩十一运夺金网站软件具有验证计划，内存感知的调试和性能分析的功能

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新思科技, Inc. 宣布该行业的可用性’s first 验证IP（VIP） 适用于Compute Express Link（CXL）2.0，旨在在数据密集型片上系统（SoC）中取得突破性的性能。 CXL是下一代开放标准互连，使生态系统能够在CPU和工作负载加速器（例如GPU，FPGA和其他专用加速器解决方案）以及内存扩展设备之间进行高速通信。该技术基于完善的PCI Express基础架构，并利用PCI Express 5.0物理和电气接口。

新思科技 VIP for CXL uses next-generation native SystemVerilog Universal Verification Methodology (UVM) architecture that enables ease of integration within existing verification environments 和 speeds up simulation performance allowing users to run a greater number of tests 和 accelerate time to the first test. VIP for CXL is natively integrated with 新思科技 Verdi Protocol 和 Performance Analyzer 和 includes built-in coverage 和 verification plans for faster verification closure. In addition, 新思科技’ silicon-proven DesignWare CXL IP 提供一个x16链接，以低延迟实现最大带宽，支持所有三种CXL协议（CXL.io，CXL.cache，CXL.mem）和设备类型，以满足特定的应用程序需求。

CXL 2.0协议为物理层和应用程序层增加了扇出，池化功能集。 CXL 2.0支持的新功能是CXL切换并支持多个逻辑设备（MLD）; CXL.io的IDE（安全性）&CXL.cache / mem;能够在APN阶段和热插拔期间协商CXL 2.0设备，可以通过CXL枚举将CXL设备视为PCI Express端点；通过QoS遥测，功能级别重置，全局持久刷新，内存交错和合规性测试断言来更新系统级可管理性

新思科技 VC VIP for CXL 2.0/1.1 is available today. DesignWare CXL IP Solution is also available now. For more information, visit CXL的VC验证IP and DesignWare CXL IP

芯片体彩十一运夺金网站软件与3纳米全栅工艺技术一起使用

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新思科技, Inc. 宣布发布3纳米（nm）全方位门（GAA）AMS体彩十一运夺金网站参考流程，该流程为体彩十一运夺金网站人员提供了一种完整的从前到后的体彩十一运夺金网站方法，以使用该体彩十一运夺金网站来体彩十一运夺金网站模拟和混合信号电路 新思科技 Custom Design Platform。它已经过优化，以使用三星3nm GAA工艺技术为高级5G，HPC，AI和IoT应用程序的体彩十一运夺金网站人员提供最大的体彩十一运夺金网站人员生产力。

Complexity at advanced nodes means designers are looking for new methods to shorten design cycles. Through close collaboration, Samsung 和 新思科技 provide a flow that is optimized to overcome design complexity 和 provide the best possible products for 3nm GAA design. Key features of the flow include in-design electromigration analysis, which shortens design closure time by providing accurate electromigration analysis before the layout is complete. It also includes Live design rule checking (DRC) with 新思科技’ IC验证器物理验证解决方案，使布局工程师可以在工作时直接从布局画布中快速检查是否违反体彩十一运夺金网站规则。

AMS参考流程为3nm GAA工艺技术的体彩十一运夺金网站提供了一种行之有效的方法。该方法论已得到三星的验证，包括一整套记录的流程和体彩十一运夺金网站实例。涵盖的主题包括体彩十一运夺金网站入门，电路仿真，蒙特卡洛分析，噪声分析，RF分析，老化和EM / IR分析，寄生仿真，布局和签核。

The 新思科技 Custom Design Platform is based on the 定制编译器 体彩十一运夺金网站和布局环境，包括HSPICE电路模拟器，FineSim电路模拟器，CustomSim FastSPICE电路模拟器，自定义WaveView波形显示，StarRC寄生提取和IC验证器物理验证。该平台具有本机集成的StarRC提取功能，可提供有关寄生虫对电路性能，性能的影响的早期反馈，并具有开创性的视觉辅助布局自动化功能，可简化高级节点布局的创建。

汽车参考流程简化了符合ISO 26262的SoC体彩十一运夺金网站

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新思科技, Inc. 三星铸造公司宣布发布经过验证的产品 汽车参考流量 to streamline 片上系统 hardware design for in-system test, implementation, verification, timing, 和 physical signoff for ISO 26262 compliance. This reference flow is targeted for automotive safety integrity level (ASIL) D autonomous driving 和 advanced driver-assistance systems (ADAS) applications. In close collaboration with Samsung, the optimized 新思科技 汽车参考流量 provides 片上系统 architects, designers, 和 verification engineers with complete differentiated design 和 IP solutions that deliver complex functional safety (FuSa) analysis, implementation, 和 verification capabilities. The 汽车参考流量 utilizes 新思科技’全面的汽车体彩十一运夺金网站流程并符合ASIL D 功能安全处理器IP.

ISO 26262 compliance complicates predictable execution of the automotive 片上系统 project, by necessitating manual time-consuming flows which lack scalability, incur significant work overhead, 和 consume limited machine resources. These challenges drive project managers 和 designers to adopt new methodologies to reduce resource requirements, minimize manual tasks, 和 improve the quality of results (QoR). Through close collaboration, Samsung Foundry 和 新思科技 delivered a comprehensive 汽车参考流量 optimized to provide the best possible productivity 和 QoR.

新思科技’ comprehensive automotive design flow includes unified functional safety verification 和 native automotive solutions, enabling designers to prove at the planning 和 implementation phases that their chip safety architecture can achieve target ASILs. Designers can perform FMEA 和 FMEDA with best-in-class technologies for unified fault campaign management. As part of the shift-left approach introduced by 新思科技, early functional safety analysis at RTL or gate-level can quickly identify candidates for triple-mode redundancy (TMR) 和 dual-core lock-step (DCLS) redundancy 和 estimate metrics for target ASIL. 新思科技 offers the industry’s first self-test solution instantiated directly into the RTL that tolerates indeterminate digital states while rapidly achieving high fault coverage. 新思科技’基于FuSa意向的本地汽车解决方案为行业提供了支持’s most comprehensive feature set to implement FuSa mechanisms, such as TMR, DCLS, 和 Finite State Machine (FSM), perform formal verification, 和 check 和 report that safety mechanisms are properly implemented. Comprehensive digital/analog fault injection 和 simulation can be performed to produce reliable metrics for FMEDA 和 roll-up. 新思科技 solutions are independently ISO 26262 certified to accelerate the deployment 和 qualification process for ASIL D designs.

The 新思科技 functional safety processor integrates hardware safety features, such as redundant processors, error-correcting code (ECC), parity protection, safety monitors, 和 user-programmable windowed watchdog timers, to detect system errors. Comprehensive documentation related to safety, including enhanced-safety manuals, FMEDA, 和 design failure modes 和 effects analysis (DFMEA) reports accelerating 片上系统-level functional safety assessments. The processor is supported by 新思科技’ ASIL D-compliant toolkit, helping software developers accelerate the development of ISO 26262-compliant codes. In addition, 新思科技 offers a broad portfolio of an automotive-grade interface, processor, 和 foundation IP that can help designers achieve high levels of functional safety, security, 和 reliability.

功能安全处理器符合ISO 26262 ASIL D要求

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新思科技, Inc. 今天宣布 DesignWare ARC EM22FS功能安全处理器 已获得完全符合ISO 26262汽车安全完整性等级（ASIL）D的认证，可满足随机硬件故障检测和系统功能安全开发流程的要求。完全合规性使公司能够加快开发和评估其汽车安全关键型SoC的过程，以根据ISO 26262标准进行随机和系统性合规。

为了满足严格的安全要求，ARC功能安全处理器提供了集成的关键安全硬件功能，包括用于内存和接口的纠错码（ECC），用于内部寄存器的瞬态故障保护，诊断错误注入以及集成的自检安全监控器。

The ASIL D compliant ARC EM22FS is a dual-core lockstep processor IP based on the ultra-compact ARC EM Processor family. The IP includes comprehensive safety documents such as failure modes, effects 和 diagnostic analysis (FMEDA), Safety Manual, Safety Case Report, ISO 26262 Functional Safety Assessment Report, 和 other safety-related documents to accelerate the functional safety analysis 和 certification of automotive 片上系统s. The ARC Functional Safety Processor IP is developed based on the ISO 9001 certified Quality Management System (QMS) for 新思科技 DesignWare IP supporting additional automotive quality requirements. The ASIL D compliant DesignWare ARC MetaWare Development Toolkit for Safety, helps software developers accelerate the development of ISO 26262 compliant code. The ARC Functional Safety Processors combined with 新思科技’ essential interface 和 foundation IP solutions in 新思科技’汽车ADAS参考体彩十一运夺金网站可帮助快速启动针对安全关键型应用的SoC体彩十一运夺金网站开发。

DesignWare ARC EM22FS功能安全处理器和ARC MetaWare安全工具包 are available now.

硅体彩十一运夺金网站套件针对高带宽内存/ PCIe /以太网连接进行了优化

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新思科技, Inc. 宣布与GLOBALFOUNDRIES合作开发广泛的 DesignWare IP for GF’的12LP + FinFET解决方案，包括USB4 / 3.2 / DPTX / 3.0 / 2.0，PCIe 5.0 / 4.0 / 2.1，芯片对芯片HBI和112G USR / XSR，112G以太网，DDR5 / 4，LPDDR5 / 4 / 4X，MIPI M -PHY，模数转换器和一次性可编程（OTP）非易失性存储器（NVM）IP。对DesignWare IP进行了优化，以满足在GF上实现的云计算和AI芯片的高带宽内存吞吐量以及可靠，高性能的连接需求’的12LP +解决方案。最近的合作标志着两家公司之间持续，成功的合作的另一个重要里程碑。

GF’GF最先进的FinFET解决方案，基于12LP +’公司已建立的14nm / 12LP平台，其中GF已出货了超过一百万个晶片。推动12LP +增强性能的功能包括：与12LP相比，将SoC级逻辑性能提高20％，在逻辑区域缩放方面提高10％。

可用性

关于DesignWare IP
新思科技 is a leading provider of high-quality, silicon-proven IP solutions for 片上系统 designs. The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, wired 和 wireless interface IP, security IP, embedded processors, 和 subsystems. To accelerate prototyping, software development, 和 integration of IP into 片上系统s, 新思科技’ IP Accelerated initiative offers IP prototyping kits, IP software development kits, 和 IP subsystems. 新思科技’IP质量方面的大量投资，全面的技术支持以及强大的IP开发方法使体彩十一运夺金网站人员能够降低集成风险并缩短产品上市时间。

统一的电子/光子体彩十一运夺金网站平台可加速光子IC体彩十一运夺金网站任务

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光电编译器新思科技, Inc. introduced its 光电编译器 光子集成电路（PIC）体彩十一运夺金网站，布局实施和验证的解决方案。 光电编译器是行业’s first unified electronic 和 photonic design platform, combining mature 和 dedicated photonic technology with 新思科技’经过行业验证的电子体彩十一运夺金网站工具和方法，使工程师能够快速，准确地生产和验证复杂的PIC体彩十一运夺金网站。通过在一个平台上提供原理图驱动的布局和先进的光子布局综合，OptoCompiler弥合了光子专家和IC体彩十一运夺金网站人员之间的鸿沟，从而使光子体彩十一运夺金网站变得可访问，快速且灵活。

光子技术正在推动数据通信，传感和成像领域的创新。随着对闪电般快速，节能通信的需求增加，集成光子学成为解决方案的关键要素。但是，到目前为止，由于许多体彩十一运夺金网站工具是用于电子而非光子学的，因此PIC的广泛实施一直受到阻碍。结果，光子体彩十一运夺金网站在很大程度上已经成为专家的领域，他们可以构建自己的工具或重新利用不同的工具集。

光电编译器将光子体彩十一运夺金网站的独特功能与业界公认的EDA功能相结合，包括：

  • 支持电子光子协同体彩十一运夺金网站，以确保可扩展的体彩十一运夺金网站流程
  • 全面的分层体彩十一运夺金网站功能，使多个体彩十一运夺金网站师可以紧密合作，以缩短产品开发周期
  • 能够使用专用的本机光子模拟器-结合行业标准的电模拟器-以获得能够说明统计差异的准确模拟结果
  • 定制光子组件的无缝体彩十一运夺金网站和仿真，可与过程体彩十一运夺金网站套件（PDK）组件一起包含在体彩十一运夺金网站中
  • 易于使用的功能，例如本机光端口和网络支持，辅助波导路由，光子电路自动对准以及曲线布局合成
  • 支持行业标准：用于脚本编写的Python，TcL和OptoDesigner和iPDK技术支持PDK开发

低功耗GNSS IP加快了物联网调制解调器的开发

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新思科技 和 Nestwave today announced a collaboration to combine Nestwave’s softcore GPS navigation IP with the 新思科技 DesignWare ARC物联网通信IP子系统 for a complete low-power global navigation satellite systems (GNSS) solution for integration into 物联网 modems. The collaboration will provide designers with a power-efficient, high-accuracy GPS solution for battery-operated devices without the additional cost of a dedicated GNSS chip. The joint solution will be presented at the 新思科技 ARC处理器虚拟峰会 2020年9月9日，星期三。

The ARC 物联网 Communications IP Subsystem is an integrated hardware 和 software solution that combines 新思科技’增强了DSP的ARC EM9D处理器，硬件加​​速器，专用外设和RF接口，可为超低带宽IoT应用提供高效的DSP性能。巢波’的GNSS解决方案利用了ARC EM9D处理器’的高效DSP功能以及使用APEX技术添加专用硬件加速器或自定义指令的能力，以降低频率要求，从而为客户提供额外的性能带宽。 MetaWare工具包支持ARC EM9D处理器，该工具包包含丰富的DSP函数库，使软件工程师可以从标准DSP构造块中快速实现算法。

Nestwave已开发出一种用于物联网应用的超低功耗，先进的全球导航卫星系统（GNSS）解决方案。当与NB-IoT，Cat M1，LoRa或Sigfox等IoT调制解调器集成时，该解决方案可为新兴应用（如资产跟踪，智能工厂和智能城市）提供低成本的地理位置，而无需外部GNSS芯片。

多晶片IC体彩十一运夺金网站软件关键在于晶片上晶片的工作

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新思科技 3DIC编译器新思科技 和 TSMC have collaborated to deliver certified design flows for advanced packaging solutions using the 新思科技 3DIC编译器 该产品既可用于基于硅中介层的基片上晶圆上芯片（CoWoS-S），也可用于基于高密度晶圆级RDL的集成扇出（InFO-R）体彩十一运夺金网站。 3DIC编译器提供当今所需的包装体彩十一运夺金网站解决方案’适用于高性能计算（HPC），汽车和移动应用的复杂多管芯系统。

The 新思科技 3DIC编译器 solution provides a unified chip-package co-design 和 analysis environment for creating an optimal 2.5D/3D multi-die system in a package. The solution includes features such as TSMC design macro support 和 auto-routing of high-density interposer based interconnects using CoWoS technology. For RDL-based InFO designs, schedules are reduced from months to a few weeks through automated DRC-aware, all-angle multilayer signal 和 power/ground routing, power/ground plane creation, 和 dummy metal insertion, along with the support for TSMC design macros.

对于CoWoS-S和InFO-R体彩十一运夺金网站，需要在封装和整个系统的背景下分析管芯。芯片感知封装和芯片感知封装的电源完整性，信号完整性和热分析对于体彩十一运夺金网站验证和签核至关重要。整合Ansys’3DIC编译器中的RedHawk系列芯片封装协同分析解决方案可以满足这一关键需求，从而实现无缝分析和更快地收敛到最佳解决方案。通过消除过度体彩十一运夺金网站，客户可以实现较小的体彩十一运夺金网站和更高的性能。

USB4 IP涵盖控制器，路由器，PHY

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DesignWare USB4 IP新思科技 today introduced the industry’s first complete DesignWare USB4 IP 该解决方案由控制器，路由器，PHY和验证IP组成。 DesignWare USB4 IP的最高工作速率为40 Gbps，是USB 3.2的最大数据速率的两倍，并向后兼容USB 3.x和USB 2.0系统。 DesignWare USB4 IP支持多种高速接口协议，包括USB4，DisplayPort 1.4a TX，PCI Express和Thunderbolt 3，可通过单个USB Type-C进行有效的数据传输并同时交付数据，电源和高分辨率视频。电缆。

新思科技 has already achieved successful test chip tapeout of its USB4 IP in an advanced 5nm FinFET process, demonstrating the robustness of the IP across process, voltage, 和 temperature variations. The new DesignWare USB4 IP is designed to meet the functionality, power, performance, 和 area requirements of a broad range of storage, PC, 和 tablet 片上系统 designs, as well as software development, debug 和 easy deployment of artificial intelligence (AI) applications at the edge. As the leading provider of USB IP for nearly two decades, 新思科技 is enabling designers to lower the risk 和 adoption barrier of integrating USB4 functionality into their 片上系统s.

The DesignWare USB4 Router IP enables efficient connectivity between all supported protocols 和 are pre-verified with the USB4 Controller IP for millions of simulated CPU hours to help ensure long-term performance 和 interoperability. The DesignWare USB4 PHY IP offers a highly efficient power profile while supporting all required protocols in approximately one-third the area of independent PHYs. The 新思科技 USB4 Verification IP Solution includes built-in coverage, protocol checkers, Verdi protocol-aware debug technology for Host 和 Device router topologies, 和 a comprehensive source code test suite for USB, PCI Express, 和 DisplayPort tunneled protocols to accelerate verification closure.

DesignWare USB4 PHYs, device router, controllers, 和 新思科技 Verification IP are available for lead customers now.

片上系统的磁带输出可帮助Arm移动处理器IP的早期采用者

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片上系统的出带新思科技 announced that 新思科技 和 Arm have collaborated to enable tapeouts of optimized system-on-chips (SoCs) for early adopters of Arm’s latest mobile processor IP, including Arm Cortex-A78 和 Cortex-X1 CPUs, 和 Mali-G78 GPU. A range of 新思科技 solutions, including the 新思科技 Fusion Design Platform, 验证连续体平台和 DesignWare接口IP，用于基于Arm的智能手机，笔记本电脑，其他移动设备，5G，增强现实和机器学习产品的体彩十一运夺金网站’s new processors. To help designers accelerate time-to-market (TTM) 和 achieve optimal power, performance, 和 area (PPA) targets, 新思科技 QuickStart Implementation Kits (QIKs) are available today.

Leveraging the collaboration that enabled successful early adopter tapeouts, the QIKs provide implementation scripts 和 reference guides 和 take advantage of 新思科技 Fusion Compiler technology to deliver enhanced PPA 和 faster turnaround. To help designers achieve their targets quickly 和 confidently, 新思科技 offers design services based on extensive experience hardening Arm processors. The services available range from QuickStart implementation through turnkey core hardening.

The 新思科技 Fusion Design Platform has been leveraged for optimized implementation of the new mobile cores 和 incorporates many 新思科技 industry-leading products, including:

  • Fusion Compiler体彩十一运夺金网站，Design Compiler NXT综合以及IC Compiler II布局布线系统，可实现高效，低功耗的体彩十一运夺金网站
  • 借助基于PrimeTime PBA的ECO（具有功率恢复和详尽的PBA）以及StarRC同时进行多角提取来完成签收关闭
  • 在Fusion Compiler和IC Compiler II布局布线中，通过RedHawk Analysis Fusion Signoff驱动的流程，对电源完整性和可靠性进行了早期加速体彩十一运夺金网站优化

Arm的早期采用者’s new premium mobile platform are using 新思科技 Verification Continuum solutions extensively with:

  • Earlier, faster, scalable software development 和 test from anywhere at any time with 新思科技 Virtualizer Development Kit (VDK) with Arm Fast Models for Cortex-A78 和 Cortex-X1 CPUs
  • 新思科技 VCS® simulation with fine-grained parallelism technology for Arm Cortex-A processors
  • 新思科技 industry-leading verification IP 和 test suites for the latest Arm AMBA® interconnect
  • 新思科技 ZeBu Server for system verification 和 benchmarking
  • 新思科技 HAPS hardware for high performance, scalable FPGA-based prototyping proven with latest Arm cores

新思科技’高质量的DesignWare接口IP支持快速开发基于Arm的移动SoC。适用于移动市场的DesignWare IP包括用于USB，DDR / LPDDR，PCI Express，MIPI，HDMI，蓝牙和移动存储接口的控制器和PHY，如今出货量达数十亿个。

关键Arm处理器的QIK现已在以下位置提供 //www.synopsys.com/臂式光电. More information about 新思科技’用于体彩十一运夺金网站基于Arm的产品的解决方案可在以下位置获得： //synopsys.com/Arm.